The present invention relates generally to timing measurement and pulse comparison circuits. The present invention relates more specifically to timing measurement and pulse comparison circuits in feedback circuits in voltage-controlled oscillators, especially voltage-controlled oscillators used in FLL (frequency locked loop) circuitry.
In electronics applications it is common to generate a desired clock signal at a frequency that is referenced to the frequency of a reference signal generated by a MRO (master reference oscillator). Phase locked loop oscillators may be used for this purpose if there is a coherent phase relationship between the clock signal and the reference signal. Sometimes, however, the clock signal generator may be of a class wherein the clock signal must be synchronized to an incoherent stimulus and then frequency locked oscillators may be used. There is a need for high performance frequency locked oscillators that can be embodied cheaply such as by using a semiconductor chip and a minimum of other component(s). Phase and/or frequency locked oscillator designs often include filters that have relatively long time constants. Thus, there is a further need for filters having long time constants, and that can be embodied cheaply, for example, by using a semiconductor chip and a minimum of other component(s).
According to one aspect of the invention, a control signal generating circuit uses a digital filter having a relatively long time constant. Digital filters having relatively long time constants may be more readily and more economically embodied on semiconductor chips than are analog filters of comparable time constants. Oscillators incorporating digital filters having relatively long time constants may be more readily and more economically embodied on semiconductor chips than are analog filters of comparable time constants.
According to a specific aspect of the invention, a feedback circuit comprising at least one ramp generator; a clocked analog to digital converter circuit located downstream of the ramp generator; a conversion circuit for generating a digital correction; and a digital low pass filter for filtering the digital correction signal to produce a filtered correction signal is provided.
According to another specific aspect of the invention, a synchronized oscillator comprising a reference clock input adapted to receive a reference clock signal; a synchronizing signal input adapted to receive a synchronizing edge; a voltage-controlled oscillator for generating an output clock signal; and a feedback circuit adapted to receive the output clock signal and the reference clock signal, the feedback circuit generating the correction signal is provided.
According to another specific aspect of the invention, a method for generating a feedback signal comprising the acts of digitizing a first difference between leading edges of a first pulse and of a second pulse; digitizing a second difference between trailing edges of the first pulse and the second pulse; differencing the first difference and the second difference to produce a third difference; and performing digital to analog conversion upon a signal derived from the third difference is provided.
According to one more specific aspect of the invention, a filter comprising an analog to digital converter, a digital filter, an oversampling modulator for lowering signal bit respresentation, a digital to analog converter and an analog low pass for smoothing is provided.
According to one further specific aspect of the invention, an effective feedback circuit is implemented entirely, or to a great extent, on silicon and with few or no external off-chip interconnects and components.
Inventive feedback circuits may, for example, replace a feedback circuitry that is part of a frequency locked loop circuit such as that disclosed in U.S. Pat. No. 6,166,606 by the same inventor as the present application.